military and commercial temperature ranges idt54/74fct821/a/b high performance cmos bus interface register 1 june 2002 military and commercial temperature ranges the idt logo is a registered trademark of integrated device technology, inc. ? 2002 integrated device technology, inc. dsc-5427/2 features: ? equivalent to amd?s am29821-25 bipolar registers in pinout/ function, speed and output drive over full temperature and voltage supply extremes ? idt54/74fct821a equivalent to fast? speed ? idt54/74fct821b 25% faster than fast ?i ol = 48ma (commercial) and 32ma (military) ? clamp diodes on all inputs for ringing suppression ? cmos power levels (1mw typ. static) ? ttl input and output compatibility ? cmos output level compatible ? substantially lower input current levels than amd?s bipolar am29800 series (5a max.) ? military product compliant to mil-std-883, class b ? available in the following packages: ? commercial: soic ? military: cerdip, lcc functional block diagram idt54/74fct821a/b high performance cmos bus interface register description: the fct821 series is built using an advanced dual metal cmos technology. the fct821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. the 74fct821 is a buffered, 10-bit wide version of the popular fct374 function. the fct821 high-performance interface family is designed for high- capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. all inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state. oe c 1 cp to nine other channels 23 1 d y d 0 q
military and commercial temperature ranges 2 idt54/74fct821/a/b high performance cmos bus interface register pin configuration symbol rating commercial military unit v term (2) terminal voltage ?0.5 to +7 ?0.5 to +7 v with respect to gnd v term (3) terminal voltage ?0.5 to v cc ?0.5 to v cc v with respect to gnd t a operating temperature 0 to +70 ?55 to +125 c t bias temperature under bia s ?55 to +125 ?65 to +135 c t stg storage temperature ?55 to +125 ?65 to +150 c p t power dissipation 0.5 0.5 w i out dc output current 120 120 ma absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed vcc by +0.5v unless otherwise noted. 2. inputs and vcc terminals only. 3. outputs and i/o terminals only. pin name i/o description dx i d flip-flop data inputs c p i clock pulse for the register. enters data into the register on the low-to-high transition y x o register 3-state outputs oe i output control. when the oe input is high, the yx outputs are in the high impedance state. when the oe input is low, the true register data is present at the yx outputs. pin description symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested. cerdip/ soic top view lcc top view logic symbol cp d oe q d cp y 10 10 2 3 1 20 19 18 15 16 9 10 d 6 d 7 d 2 d 5 d 3 d 4 d 8 23 22 24 21 17 5 6 7 4 8 d 0 v cc cp oe 13 14 11 12 d 1 gnd d 9 y 6 y 7 y 2 y 5 y 3 y 4 y 8 y 0 y 1 y 9 1 5 1 6 n c 12 1 3 1 4 g n d d 8 1 7 1 8 c p y 9 y 8 n c v c c o e d 1 d 0 y 0 y 1 y 3 nc y 4 5 6 8 7 9 10 11 1 2 8 43 2 2 7 2 6 25 24 22 23 21 20 1 9 d 5 nc d 3 d 4 d 2 d 7 d 6 index y 5 d 9 y 2 y 7 y 6
military and commercial temperature ranges idt54/74fct821/a/b high performance cmos bus interface register 3 note: 1. h = high voltage level l = low voltage level x = don?t care z = high impedance nc = no change = low-to-high transition function table (1) inputs outputs oe dx cp yx function hl z high z hh z h x x z clear lxx l h x x z hold lxx nc hl z load hh z ll l lh h notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. this parameter is guaranteed, but not tested. symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 ? ? v v il input low level guaranteed logic low level ? ? 0.8 v i ih input high current v cc = max. v i = v cc ?? 5 a v i = 2.7v ? ? 5 (4) i il input low current v cc = max. v i = 0.5v ? ? ?5 (4) a v i = gnd ? ? ?5 i ozh off state (high impedance) v cc = max. v o = v cc ?? 10 output current v o = 2.7v ? ? 10 (4) a i ozl v o = 0.5v ? ? ?10 (4) v o = gnd ? ? ?10 v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i os short circuit current v cc = max., v o = gnd (3) ?75 ?120 ? ma v oh output high voltage v cc = 3v, v in = v lc or v hc , i oh = ?32a v hc v cc ? v cc = min i oh = ?300a v hc v cc ?v v in = v ih or v il i oh = ?15ma mil 2.4 4.3 ? i oh = ?24ma com 2.4 4.3 ? v ol output low voltage v cc = 3v, v in = v lc or v hc , i ol = 300a ? gnd v lc v cc = min i ol = 300a ? gnd v lc (4) v v in = v ih or v il i ol = 32ma mil ? 0.3 0.5 i ol = 48ma com ? 0.3 0.5 dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = 0c to +70c, v cc = 5.0v 5%; military: t a = ?55c to +125c, v cc = 5.0v 10%
military and commercial temperature ranges 4 idt54/74fct821/a/b high performance cmos bus interface register power supply characteristics v lc = 0.2v, v hc = v cc - 0.2v symbol parameter test conditions (1) min. typ. (2) max. unit i cc quiescent power supply current v cc = max. ? 0.2 1.5 ma v in v hc ; v in v lc ? i cc quiescent power supply current v cc = max. ? 0.5 2 ma ttl inputs high v in = 3.4v (3) i ccd dynamic power supply v cc = max. v in v hc ? 0.15 0.25 ma/ current (4) outputs open v in v lc mhz oe = gnd one input toggling 50% duty cycle i c total power supply current (6) v cc = max. v in v hc ? 1.7 4 ma outputs open v in v lc f cp = 10mhz 50% duty cycle oe = gnd v in = 3.4v ? 2.2 6 one bit toggling v in = gnd at fi = 5mhz 50% duty cycle v cc = max. v in v hc ? 4 7.8 (5) outputs open v in v lc f cp = 10mhz 50% duty cycle oe = gnd v in = 3.4v ? 6.2 16.8 (5) eight bits toggling v in = gnd at fi = 2.5mhz 50% duty cycle notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input; (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of ? i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + ? i cc d h n t + i ccd (f cp /2+ f i n i ) i cc = quiescent current ? i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = output frequency n i = number of outputs at f i all currents are in milliamps and all frequencies are in megahertz.
military and commercial temperature ranges idt54/74fct821/a/b high performance cmos bus interface register 5 notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. these parameters are guaranteed but not tested. idt54/74fct821a idt54/74fct821b com?l. mil. com?l. mil. parameter description conditions (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. unit t plh propagation delay c l = 50pf ? 10 ? 11.5 ? 7.5 ? 8.5 ns t phl cp to yx ( oe = low) r l = 500 ? c l = 300pf (3) ? 20 ? 20 ? 15 ? 16 r l = 500 ? t su set-up time high or low, dx to cp c l = 50pf 4 ? 4 ? 3 ? 3 ? t h hold time high or low, dx to cp r l = 500 ? 2 ? 2 ? 1.5 ? 1.5 ? ns t w cp pulse width , high or low 7 ? 7 ? 6 ? 6 ? t pzh output enable time c l = 50pf ? 12 ? 13 ? 8 ? 9 ns t pzl oe to yx r l = 500 ? c l = 300pf (3) ? 23 ? 25 ? 15 ? 16 r l = 500 ? t phz output disable time c l = 5pf (3) ?7?8?6.5?7ns t plz oe to yx r l = 500 ? c l = 50pf ? 8 ? 9 ? 7.5 ? 8 r l = 500 ? switching characteristics over operating range
military and commercial temperature ranges 6 idt54/74fct821/a/b high performance cmos bus interface register pulse generator r t d.u.t . v cc v in c l v out 50pf 500 ? 500 ? 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. octal link octal link octal link octal link octal link test circuits and waveforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; z o 50 ? ; t f 2.5ns; t r 2.5ns. test switch open drain disable low closed enable low all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator.
military and commercial temperature ranges idt54/74fct821/a/b high performance cmos bus interface register 7 ordering information idt xx temp. range xxxx device type xx package x process so commercial options small outline ic high performance cmos bus inter- face register, 10-bit 54 74 ? 55 c to +125 c 0 c to +70 c d l military options cerdip leadless chip carrier blank b commercial mil-std-883, class b fct 821a 821b corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com 6/25/2002 updated as per pdns logic-00-07 and logic-01-04 data sheet document history
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